KL5BUDV003 Просмотр технического описания (PDF) - Unspecified
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KL5BUDV003 Datasheet PDF : 6 Pages
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Pin Description (PCI Mode)
KL5BUDV003
USB2.0 to PCI BUS
Pin #
QFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
I/O
Pin Name
Description
I
P_MODE[0] Burst Length select flag
I
P_MODE[1] Burst Length select flag
I
P_MODE[2] Burst Length select flag
I
TEST[0] LSI shipment test input and mode pin
I
TEST[1] LSI shipment test input and mode pin
--
VDD18
1.8V power pin
--
GND
Ground
--
AVDD
3.3V power pin
--
GND
Ground
--
AVDD
3.3V power pin
--
GND
Ground
O
REXT
USB100uA fixed reference bias current pin
O
RPU_ENA USB External pull up resistor source drive pin
--
AVDD
3.3V power pin
--
GND
Ground
--
GND
Ground
I/O
FSDP
USB FS_XVR DP pin
I/O
HSDP
USB HS_XVR DP pin
I/O
HSDM
USB HS_XVR DM pin
I/O
FSDM
USB FS_XVR DM pin
--
GND
Ground
--
GND
Ground
--
AVDD
3.3V power pin
--
VDD
3.3V power pin
--
GND
Ground
--
VDD18
1.8V power pin
--
GND
Ground
I
TEST[2] LSI shipment test input and mode pin
I
TEST[3] LSI shipment test input and mode pin
--
VDD
3.3V power pin
--
GND
Ground
O
INTAN
PCI interrupt signal
I
RSTN
PCI bus asynchronous reset input
I
CLK
PCI clock input
I
GNTN
PCI bus grant signal
O
REQN
PCI bus request signal
--
GND
Ground
I/O
AD[31]
PCI address data bus
I/O
AD[30]
PCI address data bus
I/O
AD[29]
PCI address data bus
--
VDD
3.3V power pin
--
GND
Ground
I/O
AD[28]
PCI address data bus
--
VDD18
1.8V power pin
--
GND
Ground
I/O
AD[27]
PCI address data bus
--
GND
Ground
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 2.0
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