74HC404N Просмотр технического описания (PDF) - Philips Electronics

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74HC404N

5-Bit x 64-word FIFO register; 3-state

Philips Electronics 

Philips Semiconductors

5-Bit x 64-word FIFO register; 3-state

With FIFO full; SI held HIGH in anticipation of empty location

Product specification

74HC/HCT7404

handbook, full pagewidth

SO INPUT

2 VM (1)

SI INPUT

1 VM (1)

DIR OUTPUT

t PLH

bubble - up

delay

3

tW

VM (1)

5

4

MGA660

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.8 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.

Notes to Fig.8

1. FIFO is initially full, shift-in is held HIGH

2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins

3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input

4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again

5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.

September 1993

13

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