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74HC404N

5-Bit x 64-word FIFO register; 3-state

Philips Electronics 

Philips Semiconductors

5-Bit x 64-word FIFO register; 3-state

AC WAVEFORMS

Shifting in sequence FIFO empty to FIFO full

Product specification

74HC/HCT7404

handbook, full pagewidth

1st word

1/f max

2nd word

SI INPUT

2

VM (1)

VM (1)

4

6

DIR OUTPUT

t PHL

1

tW

t PLH

5

3

64th word

7

Dn INPUT

MGA659

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.7 Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum

pulse frequency.

Notes to Fig.7

1. DIR initially HIGH; FIFO is prepared for valid data

2. SI set HIGH; data loaded into input stage

3. DIR goes LOW, input stage “busy”

4. SI set LOW; data from first location “ripple through”

5. DIR goes HIGH, status flag indicates FIFO prepared for additional data

6. Repeat process to load 2nd word through to 64th word into FIFO

DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.

September 1993

12

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