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IDT82V2048L

OCTAL T1/E1 SHORT HAUL ANALOG FRONT END

Integrated Device Technology 

IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END

INDUSTRIAL TEMPERATURE RANGES

Table-1 Pin Description (Continued)

Name

Pin No.

Type

TQFP144 PBGA160

Description

SDO: Serial Data Output

In serial host mode, the data is output on this pin. In serial write operation, SDO is always in high imped-

ance. In serial read operation, SDO is in high impedance only when SDI is in address/command byte. Data

on pin SDO is clocked out of the device on the falling edges of SCLK if pin CLKE is high, or on the rising

edges of SCLK if pin CLKE is low.

SDO/RDY/ACK

O

83

K14 RDY: Ready Output

In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be completed,

while low reports the host must insert wait states.

O

INT

Open

82

Drain

D7/AD7

28

D6/AD6

I/O

27

D5/AD5

26

D4/AD4

25

D3/AD3

High

24

D2/AD2

Imped-

23

D1/AD1

ance

22

D0/AD0

21

ACK: Acknowledge Output (Active Low)

In parallel Motorola host mode, the low level of this pin indicates that valid information on the data bus is

ready for a read operation or acknowledges the acceptance of the written data during a write operation.

INT: Interrupt (Active Low)

K13 This is an open drain, active low interrupt output. Two sources may cause the interrupt. Refer to 2.19 Inter-

rupt Handling for details.

K1

J1

J2

Dn: Data Bus 7~0

In non-multiplexed host mode, these pins are the bi-directional data bus.

J3

J4

H2

H3

G2

ADn: Address/Data Bus 7~0

In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus.

In hardware mode, these pins should be tied to VDDIO/2.

In serial host mode, these pins should be grounded.

8

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