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IDT82V2048L

OCTAL T1/E1 SHORT HAUL ANALOG FRONT END

Integrated Device Technology 

IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END

INDUSTRIAL TEMPERATURE RANGES

Table-1 Pin Description (Continued)

Name

MCLK

LOS0

LOS1

LOS2

LOS3

LOS4

LOS5

LOS6

LOS7

MODE2

Pin No.

Type

TQFP144 PBGA160

Description

MCLK: Master Clock

This is an independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048 MHz

(for E1 mode) is supplied to this pin as the clock reference of the device for normal operation.

I

10

E1

When MCLK is low, all the receivers are powered down, and the output pins RCn, RDPn and RDNn are

switched to high impedance.

In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (See Table-2

System Interface Configuration for details).

NOTE: Wait state generation via RDY/ACK is not available if MCLK is not provided.

42

K4 LOSn: Loss of Signal Output for Channel 0~7

35

K3 A high level on this pin indicates the loss of signal when there is no transition over a specified period of

75

K12 time or no enough ones density in the received signal. The transition will return to low automatically when

O

68

K11 there is enough transitions over a specified period of time with a certain ones density in the received sig-

113

E11 nal. The LOS assertion and desertion criteria are described in 2.4.3 Loss of Signal (LOS) Detection.

106

E12

3

E3

140

E4

Hardware/Host Control Interface

MODE2: Control Mode Select 2(2)

The signal on this pin determines which control mode is selected to control the device:

MODE2

Low

VDDIO/2

High

Control Interface

Hardware Mode

Serial Host Interface

Parallel Host Interface

I

(Pulled to

11

VDDIO/2)

Hardware control pins include MODE[2:0], TS[2:0], CLKE and OE.

E2

Serial host Interface pins include CS, SCLK, SDI, SDO and INT.

Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The

device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions

below for details):

MODE[2:0]

100

101

110

111

Host Interface

Non-multiplexed Motorola Mode Interface

Non-multiplexed Intel Mode Interface

Multiplexed Motorola Mode Interface

Multiplexed Intel Mode Interface

MODE1

I

43

MODE0

I

88

I

CS

(Pulled to

87

VDDIO/2)

MODE1: Control Mode Select 1(2)

K2

In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin

is low, and operates with multiplexed address and data bus when this pin is high.

In serial host mode or hardware mode, this pin should be grounded.

MODE0: Control Mode Select 0(2)

H12

In parallel host mode, the parallel host interface is configured for Motorola compatible hosts when this pin

is low, or for Intel compatible hosts when this pin is high.

In serial host mode or hardware mode, this pin should be grounded.

CS: Chip Select (Active Low)

In host mode, this pin is asserted low by the host to enable host interface. A high to low transition must

J11 occur on this pin for each read/write operation and the level must not return to high until the operation is

over.

In hardware control mode, this pin should be pulled to VDDIO/2.

2. In host mode, register e-AFE has to be set to ‘FFH’ for proper device operation. See Expanded Register Description on page 28 for more details.

6

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