IDT82V2048L Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT82V2048L

OCTAL T1/E1 SHORT HAUL ANALOG FRONT END

Integrated Device Technology 

IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END

INDUSTRIAL TEMPERATURE RANGES

2 FUNCTIONAL DESCRIPTION

2.1 OVERVIEW

The IDT82V2048L is a fully integrated octal short-haul analog front

end (AFE), which contains eight transmit and receive channels for use in

either T1 or E1 applications. The raw sliced data (no retiming) is output

to the system. Transmit equalization is implemented with low-impedance

output drivers that provide shaped waveforms to the transformer, guar-

anteeing template conformance. Moreover, testing functions, such as

JTAG boundary scan is provided. The device is optimized for flexible

software control through a serial or parallel host mode interface. Hard-

ware control is also available. Figure-1 on page 1 shows one of the eight

identical channels operation.

2.2 T1/E1 MODE SELECTION

T1/E1 mode selection configures the device globally. In Hardware

control Mode, the template selection pins TS[2:0], determine whether

the operation mode is T1 or E1 (see Table-5 on page 14). In Software

Mode, the register TS determines whether the operation mode is T1 or

E1.

2.2.1 SYSTEM INTERFACE

The system interface of each channel operates in Dual Rail Mode

with data recovery, that is, with raw data slicing only and without clock

recovery.

The Dual Rail interface consist of TDPn1, TDNn, TCLKn, RDPn,

RDNn and RCn. Data transmitted from TDPn and TDNn appears on

TTIPn and TRINGn at the line interface. The interface of the AFE is

shown in Figure-4. Pin RDPn and RDNn, are raw RZ slice outputs and

internally connected to an XOR which is fed to the RCn output for

external clock recovery applications.

2.2.1.1 SYSTEM INTERFACE CONFIGURATION

For normal transmit and receive operation, the device is configured

as follows:

In host mode, MCLK can be either clocked or pulled high. If MCLK is

pulled high, TCLK1 has to be provided for proper device operation. In

addition, register e-AFE2 has to be set to ‘FFH’ to ensure proper device

operation. See Expanded Register Description on page 28 for details.

In hardware mode, MCLK has to be pulled high and TCLK1 has to be

provided for proper device operation.

Depending on the state of TCLK1 and TCLKn, the transmitter will

Transmit All Ones (TAOS), will go into power down, or will go into high

impedance.

The status of TCLK1 and TCLKn has no effect on the receive paths.

By setting MCLK low, all the receive paths are powered down.

Table-2 summarizes the different combinations between MCLK and

TCLKn.

1. The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels.

2. The first letter ‘e-’ indicates expanded register.

11

Share Link: