IDT72V36103 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V36103
Integrated Device Technology
IDT72V36103 Datasheet PDF : 30 Pages
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IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)
Symbol
Parameter
tA
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35
tWFF Propagation Delay Time, CLKA↑ to FF/IR
tREF Propagation Delay Time, CLKB↑ to EF/OR
tPAE Propagation Delay Time, CLKB↑ to AE
tPAF Propagation Delay Time, CLKA↑ to AF
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 and CLKB↑ to MBF2
LOW or MBF1 HIGH
tPMR Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑ to A0-A35(2)
tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
tRSF Propagation Delay Time, RS1 or PRS LOW to AE LOW, AF HIGH, MBF1 HIGH
and MBF2 HIGH
tEN
Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH
to B0-B35 Active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH
or W/RB LOW to B0-B35 at high-impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
IDT72V3683L10 IDT72V3683L15
IDT72V3693L10 IDT72V3693L15
IDT72V36103L10 IDT72V36103L15
Min. Max. Min. Max. Unit
2
6.5
2
10
ns
2
6.5
2
8
ns
1
6.5
1
8
ns
1
6.5
1
8
ns
1
6.5
1
8
ns
0
6.5
0
8
ns
2
8
2
10
ns
2
6.5
2
10
ns
1
10
1
15
ns
2
6
2
10
ns
1
6
1
8
ns
9
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