IDT72V801(2014) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V801 Datasheet PDF : 16 Pages
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IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
contains four 8-bit offset registers which can be loaded with data on the inputs,
or read on the outputs. See Figure 3 for details of the size of the registers and
the default values.
If FIFO A (B) is configured to have programmable flags, when the WENA1
(WENB1) and WENA2/LDA(WENB2/LDB) are set LOW, data on the DA (DB)
inputs are written into the Empty (Least Significant Bit) Offset register on the first
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transition of WCLKA (WCLKB), into the Full (Least Significant Bit) Offset register
on the third transition, and into the Full (Most Significant Bit) Offset register on
the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the
Empty (Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing LDA (LDB) HIGH,
FIFO A (B) is returned to normal read/write operation. When LDA (LDB) is set
LOW, and WENA1 (WENB1) is LOW, the next offset register in sequence is
written.
The contents of the offset registers can be read on the QA (QB) outputs when
WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1,
RENA2(RENB1, RENB2)aresetLOW. DatacanbereadontheLOW-to-HIGH
transition of the Read Clock RCLKA (RCLKB).
A read and write should not be performed simultaneously to the offset
registers.
72V801 - 256 x 9 x 2
87
72V811 - 512 x 9 x 2
08 7
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Default Value 007H
Default Value 007H
08
8
08
1
08
(MSB)
0
87
Full Offset (LSB) Reg.
Default Value 007H
08 7
Full Offset (LSB)
Default Value 007H
08
8
08
1
00 8
(MSB)
0
72V821 - 1,024 x 9 x 2
7
0
Empty Offset (LSB) Reg.
Default Value 007H
1
0
(MSB)
00
7
0
Full Offset (LSB) Reg.
Default Value 007H
1
0
(MSB)
00
72V831 - 2,048 x 9 x 2
8
7
72V841 - 4,096 x 9 x 2
72V851 - 8,192 x 9 x 2
08
7
08
7
0
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Empty Offset (LSB)
Default Value 007H
Default Value 007H
Default Value 007H
8
2
08
3
08
4
0
(MSB)
(MSB)
(MSB)
000
0000
00000
8
7
08
7
08
7
0
Full Offset (LSB) Reg.
Full Offset (LSB)
Full Offset (LSB)
Default Value 007H
Default Value 007H
Default Value 007H
8
2
08
3
08
4
0
(MSB)
(MSB)
(MSB)
000
0000
00000
4093 drw 05
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
7
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