IDT72V801(2014) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V801 Datasheet PDF : 16 Pages
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IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS
The IDT72V801/72V811/72V821/72V831/72V841/72V851's two FIFOs, descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorresponding
referred to as FIFO A and FIFO B, are identical in every respect. The following signal names for FIFO B are provided in parentheses.
Symbol
DA0-DA8
DB0-DB8
RSA, RSB
WCLKA
WCLKB
WENA1
WENB1
WENA2/LDA
WENB2/LDB
QA0-QA8
QB0-QB8
RCLKA
RCLKB
RENA1
RENB1
RENA2
RENB2
OEA
EFA
EFB
PAEA
PAEB
PAFA
PAFB
FFA
FFB
VCC
GND
Name I/O
A Data Inputs
B Data Inputs
Reset
Write Clock
Write Enable 1
Write Enable 2/
Load
A Data Outputs
B Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
Description
I 9-bit data inputs to RAM array A.
I 9-bit data inputs to RAM array B.
I When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-
up, a reset of both FIFOs A and B is required before an initial WRITE.
I Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s)
are asserted.
I If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be
used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition
WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and
WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is
LOW.
I FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at
reset, this pin operates as a second Write Enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates
as a control to load and read the programmable flag offsets for its respective array. If the FIFO is configured to have
two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO
A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable
flags, LDA (LDB) is held LOW to write or read the programmable flag offsets.
O 9-bit data outputs from RAM array A.
O 9-bit data outputs from RAM array B.
I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1(RENB1) and
RENA2 (RENB2) are asserted.
I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH
transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to-
HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
I When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the OEB outputs DA0-
DA8 (DB0-DB8) will be in a high-impedance state.
O When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA
(EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
O When PAEA (PAEB) is LOW, FIFO A (B) is Almost-Empty based on the offset programmed into the appropriate
offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to RCLKA (RCLKB).
O When PAFA (PAFB) is LOW, FIFO A (B) is Almost-Full based on the offset programmed into the appropriate offset
register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is
HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
+3.3V power supply pin.
0V ground pin.
3
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