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IDT723676L15PF

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

Integrated Device Technology 

IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH

BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723656/723666/723676 with CLKA,

CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were

disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs

driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.

CALCULATING POWER DISSIPATION

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC2 X fo)

N

where:

N=

∆ICC =

dc =

CL =

fo

=

number of inputs driven by TTL levels

increase in power supply current for each input at a TTL HIGH level

duty cycle of inputs at a TTL HIGH level of 3.4V

output capacitance load

switching frequency of an output

300

250

200

150

100

50

0

0

fdata = 1/2 fS

TA = 25oC

CL = 0 pF

10

20

VCC = 5.0V

VCC = 5.5V

VCC = 4.5V

30

40

50

60

70

fS  Clock Frequency  MHz

80

90

5611 drw02a

Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)

8

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