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IDT723676L15PF

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

Integrated Device Technology 

IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH

BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol

SIZEB(1)

SIZEC(1)

WENC

W/RA

Name

I/O

Description

Port B

Bus Size Select

Port C

Bus Size Select

Port C Write Enable

Port A Write/

Read Select

I SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin

selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement

for ports B and C. The level of SIZEB must be static throughout device operation.

I SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin

selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement

for ports B and C. The level of SIZEC must be static throughout device operation.

I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.

I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of

CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

NOTE:

1. FS2, SIZEB and SIZEC inputs are not TTL compatible. These inputs should be tied to GND or VCC.

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