IDT723672 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723672 Datasheet PDF : 29 Pages
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CMOS SyncBiFIFOTM
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT723652
IDT723662
IDT723672
FEATURES
• Memory storage capacity:
IDT723652 – 2,048 x 36 x 2
IDT723662 – 4,096 x 36 x 2
IDT723672 – 8,192 x 36 x 2
• Supports clock frequencies up to 83MHz
• Fast access times of 8ns
• Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
• Two independent clocked FIFOs buffering data in opposite direc-
tions
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
• FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
• Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
• Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving
120-pin Thin Quad Flatpack (TQFP)
• Pin compatible to the lower density parts, IDT723622/723632/723642
• Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION
The IDT723652/723662/723672 is a monolithic, high-speed, low-power,
CMOS Bidirectional SyncFIFO (clocked) memories which support clock
frequencies up to 83MHz and have read access times as fast as 8ns. Two
independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each
chip buffer data in opposite directions. Communication between each port may
bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored.
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
FFA/IRA
AFA
Mail 1
Register
RAM
ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
FIFO 1
Status Flag
Logic
MBF1
36
EFB/ORB
AEB
FS0
FS1
A0 - A35
EFA/ORA
AEA
Programmable Flag Timing
Offset Registers
Mode
13
FIFO 2
Status Flag
Logic
Read
Write
36
Pointer
Pointer
RAM
ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
MBF2
Mail 2
Register
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FWFT
B0 - B35
FFB/IRB
AFB
36
FIFO2,
Mail2
Reset
Logic
RST2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
5609 drw 01
NOVEMBER 2003
DSC-5609/4
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