IDT723672 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723672 Datasheet PDF : 29 Pages
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IDT723652/723662/723672 CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTION
RESET
After power up, a Master Reset operation must be performed by providing
a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT723652/723662/723672 are reset separately by taking
their Reset (RST1, RST2) inputs LOW for at least four port-A Clock (CLKA) and
four port-B Clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can
switch asynchronously to the clocks. A FIFO reset initializes the internal read
and write pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output
Ready flag (ORA, ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and
the Almost-Full flag (AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox
Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a FIFO is reset,
its Input Ready flag is set HIGH after two clock cycles to begin normal operation.
A LOW-to-HIGH transition on a FIFO Reset (RST1, RST2) input latches the
value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and
Almost-Empty offset programming method. (For details see Table 1, Flag
Programming, and the Programming the Almost-Empty and Almost-Full Flags
section). The relevant FIFO Reset timing diagram can be found in Figure 2.
FIRST WORD FALL THROUGH (FWFT)
After Master Reset, the FWFT select function is active, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Reset (RST1, RST2) input is HIGH, a HIGH
on the FWFT input during the next LOW-to-HIGH transition of CLKA (for
FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode uses
the Empty Flag function (EFA, EFB) to indicate whether or not there are any
words present in the FIFO memory. It uses the Full Flag function (FFA, FFB)
to indicate whether or not the FIFO memory has any free space for writing. In
IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
Once the Reset (RST1, RST2) input is HIGH, a LOW on the FWFT input
during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for
FIFO2) will select FWFT mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at the data outputs
(A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to data outputs, no
read request necessary. Subsequent words must be accessed by performing
a formal read operation.
Following Reset, the level applied to the FWFT input to choose the desired
timing mode must remain static throughout FIFO operation. Refer to Figure 2
(Reset) for a First Word Fall Through select timing diagram.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAMMING
Four registers in these devices are used to hold the offset values for the
Almost-Empty and Almost-Full flags. The port B Almost-Empty flag (AEB) Offset
register is labeled X1 and the port A Almost-Empty flag (AEA) Offset register is
labeled X2. The port A Almost-Full flag (AFA) Offset register is labeled Y1 and
the port B Almost-Full flag (AFB) Offset register is labeled Y2. The index of each
register name corresponds to its FIFO number. The offset registers can be
loaded with preset values during the reset of a FIFO or they can be programmed
from port A (see Table 1).
FS0 and FS1 function the same way in both IDT Standard and FWFT modes.
— PRESET VALUES
To load the FIFO's Almost-Empty flag and Almost-Full flag Offset registers with
one of the three preset values listed in Table 1, at least one of the flag select inputs
must be HIGH during the LOW-to-HIGH transition of its reset input. For example,
to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be HIGH when
FlFO1 Reset (RST1) returns HIGH. Flag offset registers associated with FIFO2
are loaded with one of the preset values in the same way with FIFO2 Reset
(RST2) toggled simultaneously with FIFO1 Reset (RST1). For preset value
loading timing diagram, see Figure 2.
— PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transition of the Reset inputs. It is important to note that once parallel programming
has been selected during a Master Reset by holding both FS0 & FS1 LOW, these
inputs must remain LOW during all subsequent FIFO operation. They can only
be toggled HIGH when future Master Resets are performed and other
programming methods are desired.
After this reset is complete, the first four writes to FIFO1 do not store data in
the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2. The
port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-A0)
TABLE 1 — FLAG PROGRAMMING
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS(1)
H
H
↑
X
H
H
X
↑
H
L
↑
X
H
L
X
↑
L
H
↑
X
L
H
X
↑
L
L
↑
↑
64
X
16
X
8
X
Parallel programming via Port A(3)
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
3. If parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
10
X2 AND Y2 REGlSTERS(2)
X
64
X
16
X
8
Parallel programming via Port A(3)
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