IDT723624(2014) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723624
(Rev.:2014)

CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKA

CLKB

MRS1

BE/FWFT

SPM

FS1,FS0

FFA/IRA

EFB/ORB

tRSTS

tWFF

tRSTH

tBES

tBEH

BE

tFWS

tSPMS

tSPMH

tFSS

tFSH

0,1

tREF (3)

FWFT

tWFF

AEB

tRSF

tRSF

AFA

tRSF

MBF1

3270 drw05

NOTES:

1. FIFO2 (MRS2) Master Reset is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset (MRS1) must toggle simultaneously with MRS2.

2. PRS1 must be HIGH during Master Reset.

3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.

Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)

CLKA

CLKB

PRS1

FFA/IRA

EFB/ORB

AEB

tRSTS

tRSF

tWFF

tRSTH

tREF(3)

AFA

tRSF

tRSF

MBF1

NOTES:

1. Partial Reset is performed in the same manner for FIFO2.

2. MRS1 must be HIGH during Partial Reset.

3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 4. FIFO1 Partial Reset(1) (IDT Standard and FWFT Modes)

17

tWFF

3270 drw06

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