IDT723624(2014) Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT723624
(Rev.:2014)

CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

performing a formal read operation. Refer to Figure 3 (Master Reset) for a First

Word Fall Through select timing diagram.

Following Master Reset, the level applied to the BE/FWFT input to choose

the desired timing mode must remain static throughout FIFO operation.

PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS

Four registers in the IDT723624/723634/723644 are used to hold the offset

values for the Almost-Empty and Almost-Full flags. The Port B Almost-Empty

flag (AEB) Offset register is labeled X1 and the Port A Almost-Empty flag (AEA)

Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset register

is labeled Y1 and the Port B Almost-Full flag (AFB) Offset register is labeled Y2.

The index of each register name corresponds to its FIFO number. The offset

registers can be loaded with preset values during the reset of a FIFO,

programmed in parallel using the FIFO’s Port A data inputs, or programmed

in serial using the Serial Data (SD) input (see Table 1).

SPM, FS0/SD and FS1/SEN function the same way in both IDT Standard

and FWFT modes.

— PRESET VALUES

To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with

one of the three preset values listed in Table 1, the Serial Program Mode (SPM)

and at least one of the flag-select inputs must be HIGH during the LOW-to-HIGH

transition of its Master Reset input (MRS1, MRS2). For example, to load the

preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when

FlFO1 reset (MRS1) returns HIGH. Flag-offset registers associated with FIFO2

are loaded with one of the preset values in the same way with FIFO2 Master

Reset (MRS2), toggled simultaneously with FIFO1 Master Reset (MRS1). For

relevant preset value loading timing diagram, see Figure 3.

— PARALLEL LOAD FROM PORT A

To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master

Reset on both FlFOs simultaneously with SPM HIGH and FS0 and FS1 LOW

during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is

complete, the first four writes to FIFO1 do not store data in the RAM but load

the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by

the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723624,

IDT723634, or IDT723644, respectively. The highest numbered input is used

as the most significant bit of the binary number in each case. Valid programming

values for the registers range from 1 to 252 for the IDT723624; 1 to 508 for the

IDT723634; and 1 to 1,020 for the IDT723644. After all the offset registers are

programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is set

HIGH, and both FIFOs begin normal operation. Refer to Figure 5 for a timing

diagram illustration of parallel programming of the flag offset values.

— SERIAL LOAD

To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset

with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH

transition of MRS1 and MRS2. After this reset is complete, the X and Y register

values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH

transition of CLKA that the FS1/SEN input is LOW. There are 32-, 36-, or 40-

bit writes needed to complete the programming for the IDT723624, IDT723634,

or IDT723644, respectively. The four registers are written in the order Y1, X1,

Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1

register and the last-bit write stores the least significant bit of the X2 register. Each

register value can be programmed from 1 to 508 (IDT723624), 1 to 1,020

(IDT723634), or 1 to 2,044 (IDT723644).

When the option to program the offset registers serially is chosen, the Port

A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written.

FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit

is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFB/

IRB) flag also remains LOW throughout the serial programming process, until

all register bits are written. FFB/IRB is set HIGH by the LOW-to-HIGH transition

of CLKB after the last bit is loaded to allow normal FIFO2 operation.

See Figure 6 for Serial Programming of the Almost-Full Flag and Almost-

Empty Flag Offset Values (IDT Standard and FWFT Modes).

FIFO WRITE/READ OPERATION

The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select

(CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in the High-

TABLE 1 — FLAG PROGRAMMING

SPM FS1/SEN FS0/SD MRS1 MRS2

H

H

H

↑

X

H

H

H

↑

↑

H

H

L

↑

X

H

H

L

↑

↑

H

L

H

↑

X

H

L

H

↑

↑

H

L

L

↑

↑

L

H

L

↑

↑

L

H

H

↑

↑

L

L

H

↑

↑

L

L

L

↑

↑

NOTES:

1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

X1 AND Y1 REGlSTERS(1)

64

64

16

16

8

8

Parallel programming via Port A

Serial programming via SD

Reserved

Reserved

Reserved

11

X2 AND Y2 REGlSTERS(2)

X

64

X

16

X

8

Parallel programming via Port A

Serial programming via SD

Reserved

Reserved

Reserved

Share Link: