IDT723624(2014) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723624
(Rev.:2014)

CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are

active outputs when both CSA and W/RA are LOW.

Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH

transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is

LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs

by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA

is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and

writes on Port A are independent of any concurrent Port B operation.

The Port B control signals are identical to those of Port A with the exception

that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read

select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the

Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35

lines are in the high-impedance state when either CSB is HIGH or W/RB is

LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RB is

HIGH.

Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH

transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is

LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs

by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB

is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO reads and

writes on Port B are independent of any concurrent Port A operation.

The setup and hold time constraints to the port clocks for the port Chip Selects

and Write/Read selects are only for enabling write and read operations and

are not related to high-impedance control of the data outputs. If a port enable

is LOW during a clock cycle, the port’s Chip Select and Write/Read select may

change states during the setup and hold time window of the cycle.

When operating the FIFO in FWFT mode and the Output Ready flag is LOW,

the next word written is automatically sent to the FIFO’s output register by the

LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.

When the Output Ready flag is HIGH, subsequent data is clocked to the output

registers only when a read is selected using the port’s Chip Select, Write/Read

select, Enable, and Mailbox select.

When operating the FIFO in IDT Standard mode, the first word will cause

the Empty Flag to change state on the second LOW-to-HIGH transition of the

Read clock. The data word will not be automatically sent to the output register.

Instead, data residing in the FIFO’s memory array is clocked to the output

register only when a read is selected using the port’s Chip Select, Write/Read

select, Enable, and Mailbox select. Write and Read timing diagrams for Port

A can be found in Figure 7 and 14. Relevant Port B Write and Read cycle timing

diagrams together with Bus-Matching and Endian select operations can be

found in Figures 8 through 13.

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through at least two flip-flop

stages. This is done to improve flag-signal reliability by reducing the probability

of metastable events when CLKA and CLKB operate asynchronously to one

another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.

TABLE 2 — PORT A ENABLE FUNCTION TABLE

CSA W/RA ENA MBA CLKA

Data A (A0-A35) I/O

H

X

L

H

X

X

X

L

X

X

High-Impedance

Input

L

H

L

H

L

L

L

L

L

L

H

L

↑

H

H

↑

L

L

X

H

L

↑

L

H

X

Input

Input

Output

Output

Output

L

L

H

H

↑

Output

TABLE 3 — PORT B ENABLE FUNCTION TABLE

CSB W/RB ENB MBB CLKB

Data B (B0-B35) I/O

H

X

X

X

X

High-Impedance

L

L

L

L

L

L

L

H

L

X

X

H

L

↑

H

H

↑

L

L

X

Input

Input

Input

Output

L

H

L

H

H

L

↑

L

H

X

Output

Output

L

H

H

H

↑

Output

12

PORT FUNCTION

None

None

FIFO1 write

Mail1 write

None

FIFO2 read

None

Mail2 read (set MBF2 HIGH)

PORT FUNCTION

None

None

FIFO2 write

Mail2 write

None

FIFO1 read

None

Mail1 read (set MBF1 HIGH)

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