IDT72271LA Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72271LA Datasheet PDF : 27 Pages
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IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72261LA 16,384 x 9 BIT
8
7
0
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
IDT72271LA 32,768 x 9 BIT
8
7
0
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
5
0
8
6
0
EMPTY OFFSET (MSB) REG.
EMPTY OFFSET (MSB) REG.
00H
00H
8
7
0
8
7
0
FULL OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
5
0
8
6
0
FULL OFFSET (MSB) REG.
FULL OFFSET (MSB) REG.
00H
00H
Figure 3. Offset Register Location and Default Values
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LD
WEN
REN
SEN
WCLK
RCLK
Selection
0
0
1
0
1
0
0
1
1
X
1
1
1
0
X
1
1
X
0
1
X
X
X
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
Serial shift into registers:
28 bits for the 72261LA
30 bits for the 72271LA
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
No Operation
X
Write Memory
1
X
0
X
X
Read Memory
1
1
1
X
X
X
No Operation
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
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