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IDT72271LA

CMOS SuperSync FIFO™ 16,384 x 9 32,768 x 9

Integrated Device Technology 

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION

Symbol

Name

D0–D8

MRS

Data Inputs

Master Reset

PRS

Partial Reset

RT

Retransmit

FWFT/SI

WCLK

First Word Fall

Write Clock

WEN

RCLK

REN

OE

SEN

LD

Write Enable

Read Clock

Read Enable

Output Enable

Serial Enable

Load

DC

FF/IR

EF/OR

PAF

PAE

HF

Q0–Q8

VCC

GND

Don't Care

Full Flag/

Input Ready

Empty Flag/

Output Ready

Programmable

Almost-Full Flag

Programmable

Almost-Empty Flag

Half-Full Flag

Data Outputs

Power

Ground

I/O

Description

I Data inputs for a 9-bit bus.

I MRS initializes the read and write pointers to zero and sets the output register to all zeroes.

During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of

two programmable flag default settings, and serial or parallel programming of the offset settings.

I PRS initializes the read and write pointers to zero and sets the output method (serial or parallel),

and programmable flag settings are all retained.

I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to

LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming

method, existing timing mode or programmable flag settings. RT is useful to reread data from the

first physical location of the FIFO.

I During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial

In After Master Reset, this pin functions as a serial input for loading offset registers

I When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into

the programmable registers for parallel programming, and when enabled by SEN, the rising

edge of WCLK writes one bit of data into the programmable register for serial programming.

I WEN enables WCLK for writing data into the FIFO memory and offset registers.

I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets

from the programmable registers.

I REN enables RCLK for reading data from the FIFO memory and offset registers.

I OE controls the output impedance of Qn.

I SENenables serial loading of programmable flag offsets.

I During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023) and determines

the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to

and reading from the offset registers.

I This pin must be tied to either VCC or GND and must not toggle after Master Reset.

O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory

is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space

available for writing to the FIFO memory.

O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory

is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data

available at the outputs.

O PAF goes LOW if the number of words in the FIFO memory is more than word capacity of the FIFO

minus the full offset value m, which is stored in the Full Offset register. There are two possible default

values for m: 127 or 1,023.

O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the

Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values for n

can be programmed into the device.

O HF indicates whether the FIFO memory is more or less than half-full.

O Data outputs for a 9-bus

+5 Volt power supply pins.

Ground pins.

4

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