8405202QA Просмотр технического описания (PDF) - Intersil

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8405202QA

CMOS 16-Bit Microprocessor

Intersil 

80C86

Waveforms

CLK

(23)

TCLAV

QS0, QS1

(21) TCHSV

S2, S1, S0 (EXCEPT HALT)

(23) TCLAV

BHE/S7, A19/S6-A16/S3

TSVLH

(27)

ALE (82C88 OUTPUT)

TCLLH

(29)

NOTE

t1

(1)

TCLCL

(4) t2

TCH1CH2

t3

t4

(5)

TCL2CL1 tW

TCHCL (3)

(33)

TCLDV

TCLAX

BHE, A19-A16

TCLSH

(22)

(24)

TCHLL (31)

TCLCH

(2)

(SEE NOTE 17)

TCLAV (23)

S7-S3

TR1VCL

(8)

RDY (82C84 INPUT)

READY 80C86 INPUT)

READ CYCLE

TCLAV

(23)

AD15-AD0

RD

(41) TCHDTL

DT/R

TCLR1X

(9)

(12) TRYLCL

(11)

TRYHSH

(24) (20)

TCHRYX

TCLAX

(10)

TRYHCH

(25)

TCLAZ

(6)

TDVCL

(7)

TCLDX1

AD15-AD0

DATA IN

(37) TAZRL

(39) TCLRH

TRHAV

(40)

TCLRL

(38)

TRLRH

(45)

(42)

TCHDTH

82C88

OUTPUTS

SEE NOTES

15, 16

MRDC OR IORC

DEN

TCLML

(18)

(35) TCVNV

TCLMH

(19)

TCVNX

(36)

NOTES:

FIGURE 8A. BUS TIMING - MAXIMUM MODE (USING 82C88)

16. Signals at 82C84A or 82C88 are shown for reference only. RDY is sampled near the end of t2, t3, tW to determine if TW machine states are to

be inserted.

17. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high

82C88 CEN.

18. Status inactive in state just prior to t4.

25

FN2957.3

January 9, 2009

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