HM514170CJ-7 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM514170CJ-7

262,144-word × 16-bit Dynamic Random Access Memory

Hitachi -> Renesas Electronics 

HM514170C, HM51S4170C Series

1. Read cycle

2. Early write cycle

3. Delayed write cycle

4. Read-modify-write cycle

5. RAS-only refresh cycle

6. CAS-before-RAS refresh cycle

7. Self refresh cycle (HM51S4170C)

8. Fast page mode read cycle

9. Fast page mode early write cycle

10. Fast page mode delayed write cycle

11. Fast page mode read-modify-write cycle

Inputs

RAS

CAS

UWE

LWE

Output

Operation

H

H

D

D

Open

Standby

H

L

H

H

Valid

Standby

L

L

H

H

Valid

Read cycle

L

L

L*2

L*2

Open

Early write cycle

L

L

L*2

L*2

Undefined

Delayed write cycle

L

L

H to L

H to L

Valid

Read-modify-write cycle

L

H

D

D

Open

RAS-only refresh cycle

H to L

L

D

D

Open

CAS-before-RAS refresh cycle

Self refresh cycle (HM51S4170C)

L

H to L

H

H

Valid

Fast page mode read cycle

L

H to L

L*2

L*2

Open

Fast page mode early write cycle

L

H to L

L*2

L*2

Undefined

Fast page mode delayed write cycle

L

H to L

H to L

H to L

Valid

Fast page mode read modify-write cycle

Notes: 1. H: High (inactive) L: Low (active) D: H or L

2. tWCS ≥ 0 ns Early write cycle

tWCS < 0 ns Delay write cycle

3. Mode is determined by the OR function of the UWE and LWE. (Mode is set by the earliest of

UWE and LWE active edge and reset by the latest of UWE and LWE inactive edge.) However

write OPERATION and output HIZ control are done independently by each UWE, LWE.

5

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