HM514170CJ-7 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics
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HM514170CJ-7 Datasheet PDF : 26 Pages
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HM514170C, HM51S4170C Series
Self refresh Mode
HM51S4170C
-7
-8
Parameter
Symbol Min Max Min Max Unit Notes
RAS pulse width (self refresh)
t RASS
100 —
100 —
µs 23, 24,
25
RAS precharge time (self refresh)
t RPS
130 — 150 — ns
CAS hold time (self refresh)
t CHS
–50 —
–50 —
ns
Notes: 1. AC measurements assume tT = 5 ns.
2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not
referred to output voltage levels.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as
a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC.
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as
a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
10. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only: if tWCS ≥ tWCS (min), the cycle is an early write cycle and
the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥
tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-
write and the data output will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading
edge in a delayed write or a read-modify-write cycle.
12. tRASC defines RAS pulse width in fast page mode cycles.
13. Access time is determined by the longer of tAA or tCAC or tACP.
14. After power up pause for 100 µs, then DRAM initialization requires a minimum of eight RAS
only refresh or eight CAS-before-RAS refresh cycles. If the user will implement CAS-before-
RAS timing in their system, then the eight initialization cycles MUST be CAS-before-RAS
cycles
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
16. Either tRCH or tRRH must be satisfied for a read cycle.
17. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS
pins must be on the same level.
18. A word of data can be written only when UWE and LWE go low at the same time. This implies
that early write cycles cannot be combined with delayed write cycles in the same cycles
because all data is latched at the fall of the first WE. In other words, staggering the WE signals
in one cycle is not permitted.
19. tRCH, tRRH, tWCS, tRWD, tCWD and tAWD are determined by the earlier falling edge of UWE and LWE.
20. tWCH and tRCS are determined by the later rising edge of UWE or LWE.
21. tWP, tRWL, tCWL, tOEH, tDS, tDH and tCPW should be satisfied by both UWE and LWE.
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