HEF4011UB Просмотр технического описания (PDF) - Philips Electronics
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HEF4011UB Datasheet PDF : 8 Pages
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Philips Semiconductors
Quadruple 2-input NAND gate
Product specification
HEF4011UB
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL TYP. MAX.
Propagation delays
In → On
HIGH to LOW
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
Input capacitance
5
10
tPHL
15
5
10
tPLH
15
5
10
tTHL
15
5
10
tTLH
15
CIN
60
120 ns
25
50 ns
20
40 ns
35
70 ns
20
40 ns
17
35 ns
75
150 ns
30
60 ns
20
40 ns
60
110 ns
30
60 ns
20
40 ns
10 pF
TYPICAL EXTRAPOLATION
FORMULA
25 ns + (0,70 ns/pF) CL
12 ns + (0,27 ns/pF) CL
10 ns + (0,20 ns/pF) CL
8 ns + (0,55 ns/pF) CL
9 ns + (0,23 ns/pF) CL
9 ns + (0,16 ns/pF) CL
15 ns + (1,20 ns/pF) CL
6 ns + (0,48 ns/pF) CL
4 ns + (0,32 ns/pF) CL
10 ns + (1,00 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
500 fi + ∑ (foCL) × VDD2
where
10
5 000 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
25 000 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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