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HCF4034

INPUT/OUTPUT BUS REGISTER 8-STAGE STATIC BIDIRECTIONAL PARALLEL/SERIAL

STMicroelectronics 

HCC/HCF4034B

8-STAGE STATIC BIDIRECTIONAL PARALLEL/SERIAL

INPUT/OUTPUT BUS REGISTER

. BIDIRECTIONAL PARALLEL DATA INPUT

. PARALLEL OR SERIAL INPUTS/PARALLEL

OUTPUTS

. ASYNCHRONOUS OR SYNCHRONOUS PAR-

ALLEL DATA LOADING

. PARALLEL DATA-INPUT ENABLE ON ”A”

DATA LINES (3-state output)

. DATA RECIRCULATION FOR REGISTER EX-

PANSION

. MULTIPACKAGE REGISTER EXPANSION

. FULLY STATIC OPERATIONAL DC-TO-5MHz

(typ.) AT VDD = 10V

. QUIESCENT CURRENT SPECIFIED TO 20V

FOR HCC DEVICE

. 5V, 10V, AND 15V PARAMETRIC RATINGS

. INPUT CURRENT OF 100nA AT 18V AND 25°C

FOR HCC DEVICE

. 100% TESTED FOR QUIESCENT CURRENT

. MEETS ALL REQUIREMENTS OF JEDECTEN-

TATIVE STANDARD N° 13A, ”STANDARD SPE-

CIFICATIONS FOR DESCRIPTION OF ”B”

SERIES CMOS DEVICES”

EY

F

(Plastic Package) (Ceramic Frit Seal Package)

M1

(Micro Package)

ORDER CODES :

HCC4034BF

HCF4034BEY

HCF4034BM1

PIN CONNECTIONS

DESCRIPTION

The HCC4034B (extended temperature range) and

HCF4034B (intermediate temperature range) are

monolithic integrated circuits, available in 24-lead

dual in-line plastic or ceramic package and plastic

micro package. The HCC/HCF4034B is a static

eight-stage parallel-or serial-input parallel-output

register. It can be used to : 1) bidirectionally transfer

parallel information between two buses ; 2) convert

serial data to parallel form and direct the parallel

data to either of twobuses ; 3) store (recirculate) par-

allel data, or 4) accept parallel data from either of two

buses and convert that data to serial form. Inputs

that control the operations include a single-phase

CLOCK (CL), A DATA ENABLE (AE), ASYN-

CHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-

B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/

SERIAL (P/S). Data inputs include 16 bidirectional

parallel data lines of which the eight A data lines are

inputs (3-state outputs) and the B data lines are out-

puts (inputs) depending on the signal level on the

A/B input. In addition, an input for SERIAL DATA is

also provided. All register stages are D-type master-

slave flip-flops with separate master and slave clock

June 1989

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