HB52RF649DC Просмотр технического описания (PDF) - Elpida Memory, Inc
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HB52RF649DC Datasheet PDF : 16 Pages
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HB52RF649DC-B, HB52RD649DC-B
Serial PD Matrix*1
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes used by module
manufacturer
1
0
0
0
0
0
0
0
80
Total SPD memory size
0 0 0 0 1 0 0 0 08
Memory type
0 0 0 0 0 1 0 0 04
Number of row addresses bits
0 0 0 0 1 1 0 1 0D
Number of column addresses bits 0 0 0 0 1 0 1 0 0A
Number of banks
0 0 0 0 0 0 1 0 02
Module data width
0 1 0 0 1 0 0 0 48
Module data width (continued)
0 0 0 0 0 0 0 0 00
Module interface signal levels
0 0 0 0 0 0 0 1 01
SDRAM cycle time
(highest /CE latency)
(-75) 7.5ns
0 1 1 1 0 1 0 1 75
(-A6) 10ns
1 0 1 0 0 0 0 0 A0
SDRAM access from Clock (highest
/CE latency)
0 1 0 1 0 1 0 0 54
(-75) 5.4ns
(-A6) 6ns
0 1 1 0 0 0 0 0 60
Module configuration type
0 0 0 0 0 0 1 0 02
Refresh rate/type
1 0 0 0 0 0 1 0 82
SDRAM width
0 0 0 0 1 0 0 0 08
Error checking SDRAM width
0 0 0 0 1 0 0 0 08
SDRAM device attributes:
minimum clock delay for back-to- 0 0 0 0 0 0 0 1 01
back random column addresses
SDRAM device attributes:
Burst lengths supported
0 0 0 0 1 1 1 1 0F
SDRAM device attributes: number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04
SDRAM device attributes:
/CE latency
0 0 0 0 0 1 1 0 06
SDRAM device attributes:
/S latency
0 0 0 0 0 0 0 1 01
SDRAM device attributes:
/W latency
0 0 0 0 0 0 0 1 01
SDRAM module attributes
0 0 0 0 0 0 0 0 00
SDRAM device attributes: General 0 0 0 0 1 1 1 0 0E
SDRAM cycle time
(2nd highest /CE latency)
10ns
1 0 1 0 0 0 0 0 A0
SDRAM access from Clock (2nd
highest /CE latency)
6ns
0 1 1 0 0 0 0 0 60
SDRAM cycle time
(3rd highest /CE latency)
Undefined
0 0 0 0 0 0 0 0 00
Comments
128
256byte
SDRAM
13
10
2
72
0 (+)
LVTTL
CL = 3
ECC
Normal
(7.8125µs)
Self refresh
×8
×8
1 CLK
1, 2, 4, 8
4
2, 3
0
0
Unbuffer
VCC ± 10%
CL = 2
Data Sheet E0223H30 (Ver. 3.0)
4
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