GL811S Просмотр технического описания (PDF) - GENESYS LOGIC

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GL811S

USB2.0 to ATA / ATAPI Bridge Controller

GENESYS LOGIC 

GL811S USB2.0 to ATA/ATAPI Bridge Controller

CHAPTER 5 FUNCTION DESCRIPTION

5.1 UTM

The USB 2.0 Transceiver Macrocell, it’s the analog circuitry that handles the low level USB protocol and

signaling, and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the

general logic.

5.2 SIE

The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing

and state machine logic to handle USB packets and transactions.

5.3 EP0/EP3 FIFO

Endpoint 0/3 FIFO: The Control and Interrupt FIFO. It is composed of TX03FIFO and RX03FIFO, with

64-byte FIFO each, and it is used for endpoint 0/3 data transfer.

5.4 Bulk FIFO

It is constructed in interleaved architecture and composed by two data buffers which is used to store data

transferred between USB host and IDE device.

5.5 IDE Interface

The IDE engine is extended from standard ATA / ATAPI protocol. It supports multiword DMA mode, and ultra

DMA mode data transfers.

5.6 Operation Register

It is a register space to store status information and to control the functions of GL811S by 8051.

5.7 SPI Interface

The Serial Peripheral Interface is a serial, synchronous communication protocol. It is compatible with

Motorola’s SPI specifications.

©2007 Genesys Logic Inc. - All rights reserved.

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