DS1073 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1073

3V EconOscillator/Divider

Dallas Semiconductor -> Maxim Integrated 

DS1073

OPERATION OF OUTPUT ENABLE

Since the output enable, internal master oscillator and/or external master oscillator are likely all

asynchronous there is the possibility of timing difficulties in the application. To minimize these

difficulties the DS1073 features an “enabling sequencer” to produce predictable results when the device is

enabled and disabled. In particular the output gating is configured so that truncated output pulses can

never be produced.

ENABLE TIMING

The output enable function is produced by sampling the OE input with the output from the prescaler mux

(MCLK) and gating this with the output from the programmable divider. The exact behavior of the

device is therefore dependent on the setup time (tSU) from a transition on the OE input to the rising edge

of MCLK. If the actual setup time is less than tSUEM, then one more complete cycle of MCLK will be

required to complete the enable or disable operation (see diagrams). This is unlikely to be of any

consequence in most applications, and then only if the value for N is small. In general, the output will

make its first positive transition between approximately one and two clock periods of MCLK after the

rising edge of OE.

Figure 4

tM = PERIOD OF MCLK

td = PROP DELAY FROM MCLK ­ TO OUT ­

MAX VALUE OF ten = tSUEM + 2 tM + td

MIN VALUE OF ten = tSUEM + tM + td

DISABLE TIMING

If OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If

OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE

and the rising edge of MCLK. If tSU < tSUEM the result will be one additional pulse appearing on the

output before disabling occurs.

If the device is in divide-by-one mode, the disabling occurs slightly differently. In this case if tSU > tSUEM

one additional output pulse will appear, if tSU < tSUEM then two additional output pulses will appear.

The following diagrams illustrate the timing in each of these cases.

Figure 5

tM = PERIOD OF MCLK

td = PROP DELAY FROM MCLK ­ TO OUT ­

tOUTH = WIDTH OF OUTPUT PULSE

MAX VALUE OF tdis = tSUEM + td + tOUTH

MIN VALUE OF tdis = 0

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