DM9000B Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.

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DM9000B

Ethernet Controller With General Processor Interface

Davicom Semiconductor, Inc. 

DM9000B

Ethernet Controller with General Processor Interface

6.11 RX/TX Flow Control Register ( 0AH )

Bit

Name

Default

Description

TX Pause Packet

7

TXP0

PS0,RW Auto clears after pause packet transmission completion. Set to TX pause packet

with time = 0000h

TX Pause packet

6

TXPF

PS0,RW Auto clears after pause packet transmission completion. Set to TX pause packet

with time = FFFFH

5

TXPEN

PS0,RW

Force TX Pause Packet Enable

Enables the pause packet for high/low water threshold control

Back Pressure Mode

4

BKPA

PS0,RW This mode is for half duplex mode only. It generates a jam pattern when any

packet comes and RX SRAM is over BPHW of register 8.

Back Pressure Mode

3

BKPM

PS0,RW This mode is for half duplex mode only. It generates a jam pattern when a packet’s

DA matches and RX SRAM is over BPHW of register 8.

2

RXPS

PS0,R/C RX Pause Packet Status, latch and read clearly

1

RXPCS PS0,RO RX Pause Packet Current Status

0

FLCE

PS0,RW

Flow Control Enable

Set to enable the flow control mode (i.e. can disable DM9000B TX function)

6.12 EEPROM & PHY Control Register ( 0BH )

Bit

Name

Default

Description

7:6 RESERVED 0,RO Reserved

5

REEP

P0,RW Reload EEPROM. Driver needs to clear it up after the operation completes

4

WEP

P0,RW Write EEPROM Enable

3

EPOS

P0,RW

EEPROM or PHY Operation Select

When reset, select EEPROM; when set, select PHY

2

ERPRR

P0,RW

EEPROM Read or PHY Register Read Command. Driver needs to clear it up after

the operation completes.

1

ERPRW

P0,RW

EEPROM Write or PHY Register Write Command. Driver needs to clear it up after

the operation completes.

0

ERRE

P0,RO

EEPROM Access Status or PHY Access Status

When set, it indicates that the EEPROM or PHY access is in progress

6.13 EEPROM & PHY Address Register ( 0CH )

Bit

Name

Default

Description

7:6

PHY_ADR

P01,RW

PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 in

application.

5:0

EROA

P0,RW EEPROM Word Address or PHY Register Number.

6.14 EEPROM & PHY Data Register (EE_PHY_L:0DH EE_PHY_H:0EH)

Bit

Name

Default

Description

7:0

EE_PHY_L

P0,RW

EEPROM or PHY Low Byte Data

The low-byte data read from or write to EEPROM or PHY.

7:0

EE_PHY_H

P0,RW

EEPROM or PHY High Byte Data

The high-byte data read from or write to EEPROM or PHY.

Final

18

Version: DM9000B-13-DS-F02

June 4, 2009

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