DM9000B Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.

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DM9000B

Ethernet Controller With General Processor Interface

Davicom Semiconductor, Inc. 

DM9000B

Ethernet Controller with General Processor Interface

6

RLCP

P0,RW

Retry Late Collision Packet

Re-transmit the packet with late-collision

5

DTU

P0,RW

Disable TX Under run Retry

Disable to re-transmit the underruned packet

One Packet Mode

When set, only one packet transmit command can be issued before transmit

4

ONEPM P0,RW completed.

When cleared, at most two packet transmit command can be issued before

transmit completed.

Inter-Frame Gap Setting

0XXX: 96-bit

1000: 64-bit

1001: 72-bit

3~0

IFGS

P0,RW

1010:80-bit

1011:88-bit

1100:96-bit

1101:104-bit

1110: 112-bit

1111:120-bit

6.26 Operation Test Control Register ( 2EH )

Bit

Name

Default

Description

System Clock Control

Set the internal system clock.

7~6

SCC

P0,RW

00: 50Mhz

01: 20MHz

10: 100MHz

11: Reserved

5 RESERVED P0,RW Reserved

4

SOE

P0,RW Internal SRAM Output-Enable Always ON

3

SCS

P0,RW Internal SRAM Chip-Select Always ON

2~0

PHYOP

P0,RW Internal PHY operation mode for testing

6.27 Special Mode Control Register ( 2FH )

Bit

Name

Default

7

SM_EN

P0,RW Special Mode Enable

6~3 RESERVED P0,RW Reserved

2

FLC

P0,RW Force Late Collision

1

FB1

P0,RW Force Longest Back-off time

0

FB0

P0,RW Force Shortest Back-off time

Description

Final

21

Version: DM9000B-13-DS-F02

June 4, 2009

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