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DM9000B

Ethernet Controller With General Processor Interface

Davicom Semiconductor, Inc. 

DM9000B

Ethernet Controller with General Processor Interface

6.8 Receive Overflow Counter Register ( 07H )

Bit

Name

Default

Description

7

RXFU

PS0,R/C

Receive Overflow Counter Overflow

This bit is set when the ROC has an overflow condition

6:0

ROC

PS0,R/C

Receive Overflow Counter

This is a statistic counter to indicate the received packet count upon FIFO overflow

6.9 Back Pressure Threshold Register (08H)

Bit

Name

Default

Description

Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern

7:4

BPHW

PS3, RW

when RX SRAM free space is lower than this threshold value

The default is 3K-byte free space. Please do not exceed SRAM size

(1 unit=1K bytes)

Jam Pattern Time. Default is 200us

bit3 bit2 bit1 bit0 time

0000

5us

0001

0010

0011

10us

15us

25us

0100

50us

0 1 0 1 100us

3:0

JPT

PS7, RW

0110

0111

150us

200us

1 0 0 0 250us

1 0 0 1 300us

1 0 1 0 350us

1 0 1 1 400us

1 1 0 0 450us

1 1 0 1 500us

1 1 1 0 550us

1 1 1 1 600us

6.10 Flow Control Threshold Register ( 09H )

Bit

Name

Default

Description

RX FIFO High Water Overflow Threshold

Send a pause packet with pause_ time=FFFFH when the RX RAM free space is

7:4

HWOT PS3, RW less than this value., If this value is zero, its means no free RX SRAM space. The

default value is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K

bytes)

RX FIFO Low Water Overflow Threshold

Send a pause packet with pause time=0000 when RX SRAM free space is larger

3:0

LWOT

PS8, RW

than this value. This pause packet is enabled after the high water pause packet is

transmitted. The default SRAM free space is 8K-byte. Please do not exceed SRAM

size

(1 unit=1K bytes)

Final

17

Version: DM9000B-13-DS-F02

June 4, 2009

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