CY7C135-25JC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C135-25JC

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

Cypress Semiconductor 

Switching Waveforms

Read Cycle No. 1[11,12]

ADDRESS

DATA OUT

tOHA

PREVIOUS DATA VALID

Either Port Address Access

tRC

tAA

CY7C135

CY7C1342

DATA VALID

Read Cycle No. 2[11,13]

SEM [10]or CE

OE

DATA OUT

tPU

ICC

ISB

Either Port CE/OE Access

tACE

tLZOE

tLZCE

tDOE

tHZOE

DATA VALID

Read Timing with Port-to-Port[14]

ADDRESSR

R/WR

twc

MATCH

tPWE

DATAINR

tSD

tHD

VALID

tHZCE

tPD

ADDRESSL

MATCH

DATAOUTL

Notes:

11. R/W is HIGH for read cycle.

12. Device is continuously selected, CE = VIL and OE = VIL.

13. Address valid prior to or coincident with CE transition LOW.

14. CEL = CER =LOW; R/WL = HIGH

tDDD

tWDD

VALID

Document #: 38-06038 Rev. *C

Page 6 of 12

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