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CY7C130A

1 K × 8 Dual-Port Static RAM

Cypress Semiconductor 

Switching Characteristics

Over the Operating Range[23, 24] (continued)

Parameter

Description

Busy/Interrupt Timing

tBLA

BUSY LOW from address match

tBHA

BUSY HIGH from address mismatch[30]

tBLC

tBHC

BUSY LOW from CE LOW

BUSY HIGH from CE HIGH[30]

tPS

tWB[31]

Port set-up for priority

R/W LOW after BUSY LOW

tWH

R/W HIGH after BUSY HIGH

tBDD

BUSY HIGH to valid data

tDDD

Write data valid to read data valid

tWDD

Write pulse to data delay

Interrupt Timing

tWINS

tEINS

tINS

tOINR

tEINR

tINR

R/W to INTERRUPT set time

CE to INTERRUPT set time

Address to INTERRUPT set time

OE to INTERRUPT reset time[20]

CE to INTERRUPT reset time[20]

Address to INTERRUPT reset time[20]

CY7C130, CY7C130A

CY7C131, CY7C131A

7C130-35

7C131-35

7C140-35

7C141-35

Min Max

7C130-45

7C131-45

7C140-45

7C141-45

Min Max

7C130-55

7C131-55

7C140-55 Unit

7C141-55

Min Max

–

20

–

25

–

30 ns

–

20

–

25

–

30 ns

–

20

–

25

–

30 ns

–

20

–

25

–

30 ns

5

–

5

–

5

–

ns

0

–

0

–

0

–

ns

30

–

35

–

35

–

ns

–

35

–

45

–

45 ns

– Note 32 – Note 32 – Note 32 ns

– Note 32 – Note 32 – Note 32 ns

–

25

–

35

–

45 ns

–

25

–

35

–

45 ns

–

25

–

35

–

45 ns

–

25

–

35

–

45 ns

–

25

–

35

–

45 ns

–

25

–

35

–

45 ns

Notes

30. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.

31. CY7C140/CY7C141 only.

32. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:

BUSY on Port B goes HIGH.

Port B’s address is toggled.

CE for Port B is toggled.

R/W for Port B is toggled during valid read.

Document Number: 38-06002 Rev. *H

Page 10 of 22

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