CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Waveforms
ADDRESS
DATA OUT
tOHA
PREVIOUS DATAVALID
Figure 5. Read Cycle No. 1[33, 34]
Either Port Address Access
tRC
tAA
DATA VALID
CE
OE
DATA OUT
ICC
ISB
Figure 6. Read Cycle No. 2[33, 35]
Either Port CE/OE Access
tACE
tLZOE
tLZCE
tDOE
tPU
tHZOE
DATA VALID
tHZCE
tPD
Figure 7. Read Cycle No. 3[34]
ADDRESSR
R/WR
DINR
Read with BUSY, Master: CY7C130 and CY7C131
tRC
ADDRESS MATCH
tPWE
tHD
VALID
ADDRESSL
BUSYL
DOUTL
tPS
tBLA
ADDRESS MATCH
tBHA
tBDD
tWDD
tDDD
VALID
Notes
33. R/W is HIGH for read cycle.
34. Device is continuously selected, CE = VIL and OE = VIL.
35. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-06002 Rev. *H
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