CY7C1009-15VCT(1998) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1009-15VCT
(Rev.:1998)

128K x 8 Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]

ADDRESS

CE1

CE2

WE

DATA I/O

tSA

tAW

tWC

tSCE

tPWE

tSCE

tSD

DATA VALID

tHA

tHD

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]

ADDRESS

CE1

tWC

tSCE

CE2

tSCE

tAW

tHA

tSA

tPWE

WE

OE

DATA I/O

NOTE 15

tHZOE

tSD

tHD

DATAIN VALID

Notes:

13. Data I/O is high impedance if OE = VIH.

14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.

CY7C109

CY7C1009

109–8

109–9

7

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