CY7C007A(2010) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C007A Datasheet PDF : 22 Pages
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CY7C007A32 K/16 K × 8, 16 K × 9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
32 K/16 K × 8, 16 K × 9
Dual-Port Static RAM
32 K/16 K × 8, 16 K × 9 Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 16 K × 8 organization (CY7C006A)
■ 32 K × 8 organization (CY7C007A)
■ 16 K × 9 organization (CY7C016A)
■ 32 K × 9 organization (CY7C017A)
■ 0.35-micron CMOS for optimum speed/power
■ High-speed access: 12[1]/15/20 ns
■ Low operating power
❐ Active: ICC = 180 mA (typical)
❐ Standby: ISB3 = 0.05 mA (typical)
■ Fully asynchronous operation
Logic Block Diagram
R/WL
CEL
OEL
■ Automatic power-down
■ Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Pin select for Master or Slave
■ Commercial temperature range
■ Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP
(CY7C007A and CY7C016A)
■ Pb-Free packages available
R/WR
CER
OER
[2]
8/9
I/O0L–I/O7/8L
I/O
Control
I/O
Control
8/9
[2]
I/O0R–I/O7/8R
A0L–A13/1[44L]
14/15
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
14/15
A0R–A13/14[R4]
A0L–A13/14[4L]
14/15
CEL
OEL
R/WL
SEML
BUSYL [3]
INTL
Notes
1. See page 7 for Load Conditions.
2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
3. BUSY is an output in master mode and an input in slave mode.
4. A0–A13 for 16K; A0–A14 for 32K devices.
Interrupt
Semaphore
Arbitration
M/S
14/15
A0R–A13/14R[4]
CER
OER
R/WR
SEMR
[3] BUSYR
INTR
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06045 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 17, 2010
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