CY7C007A(2010) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C007A Datasheet PDF : 22 Pages
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics
Over the Operating Range[14] (continued)
Parameter
Description
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-Up for Priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[23]
BUSY HIGH to Data Valid
INTERRUPT TIMING[24]
tINS
INT Set Time
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
tSAA
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
–12[15]
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–15
Unit
–20
Min Max Min Max Min Max
12
15
20
ns
12
15
17
ns
5
5
5
ns
0
0
0
ns
11
13
15
ns
12
15
20
ns
12
15
20
ns
12
15
20
ns
10
10
10
ns
5
5
5
ns
5
5
5
ns
12
15
20
ns
Data Retention Mode
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
designed with battery backup in mind. Data retention voltage and
supply current are guaranteed over temperature. The following
rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 V).
Timing
VCC
CE
Data Retention Mode
4.5V VCC 2.0V
4.5V
tRC
VCC to VCC – 0.2V
VIH
Parameter
ICCDR1
Test Conditions[25]
@ VCCDR = 2 V
Max Unit
1.5
mA
Notes:
23. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
24. Test conditions used are Load 2.
25. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested.
Document Number: 38-06045 Rev. *F
Page 10 of 22
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