CY7C007A(2010) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C007A
(Rev.:2010)

32 K/16 K × 8, 16 K × 9 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle No. 1 (Either Port Address Access)[26, 27, 28]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (Either Port CE/OE Access)[26, 29, 30]

CE

tACE

OE

DATA OUT

ICC

CURRENT ISB

tDOE

tLZOE

tLZCE

tPU

Read Cycle No. 3 (Either Port)[26, 28, 29, 30]

ADDRESS

tRC

tAA

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

CY7C006A/CY7C007A

CY7C016A/CY7C017A

DATA VALID

tOHA

tHZCE

tHZOE

DATA VALID

tPD

tOHA

tHZCE

Notes

26. R/W is HIGH for read cycles.

27. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.

28. OE = VIL.

29. Address valid prior to or coincident with CE transition LOW.

30. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

Document Number: 38-06045 Rev. *F

Page 11 of 22

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