CS5521(2000) Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

Список матч

CS5521
(Rev.:2000)

16-Bit or 24-Bit, 2/4/8-Channel ADCs with PGIA

Cirrus Logic 

CS5521/22/23/24/28

2.2.1 System Initialization

When power to the CS5521/22/23/24/28 is applied,

the chips are held in a reset condition until the

32.768 kHz oscillator has started and a counter-

timer elapses. Due to the high Q of the 32.768 kHz

crystal, the oscillator takes 400-600 ms to start. The

counter-timer counts 2006 oscillator clock cycles

to make sure the oscillator is fully stable. During

this time-out period the serial port logic is reset and

the RV (Reset Valid) bit in the configuration regis-

ter is set to indicate that a valid reset occurred. Af-

ter a reset, the on-chip registers are initialized to the

following states and the converter is placed in the

command mode where it waits for a valid com-

mand.

configuration register:

offset registers:

gain registers:

channel setup registers:

000040(H)

000000(H)

400000(H)

000000(H)

Note: A system reset can be initiated at any time by writing

a logic 1 to the RS (Reset System) bit in the configura-

tion register. After a reset, the RV bit is set until the

configuration register is read. The user must then

write a logic 0 to the RS bit to take the part out of the

reset mode. Any other bits written to the configuration

register at this time will be lost. The configuration reg-

ister must be written again once RS = 0 to set any other

bits.

2.2.2 Serial Port Initialization Sequence

The serial port is initialized to the command mode

whenever a power-on reset is performed inside the

converter, or when the user transmits the port ini-

tialization sequence. The port initialization se-

quence involves clocking 15 bytes of all 1’s,

followed by one byte with the following bit con-

tents ‘11111110’. This sequence places the chip in

the command mode where it waits for a valid com-

mand to be written.

18

DS317F2

Share Link: