CS5521(2000) Просмотр технического описания (PDF) - Cirrus Logic
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CS5521 Datasheet PDF : 56 Pages
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CS5521/22/23/24/28
SWITCHING CHARACTERISTICS (TA = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;
Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF.))
Parameter
Symbol Min
Typ
Max Unit
Master Clock Frequency
(Note 25) XIN
External Clock or Internal Oscillator (CS5522/24/28)
(CS5521/23)
Master Clock Duty Cycle
30 32.768 200 kHz
30 32.768 130 kHz
40
-
60
%
Rise Times
(Note 26)
trise
Any Digital Input Except SCLK
SCLK
Any Digital Output
-
-
1.0
µs
-
-
100
µs
-
50
-
ns
Fall Times
Start-up
(Note 26)
tfall
Any Digital Input Except SCLK
SCLK
Any Digital Output
-
-
1.0
µs
-
-
100
µs
-
50
-
ns
Oscillator Start-up Time XTAL = 32.768 kHz (Note 27) tost
Power-on Reset Period
tpor
Serial Port Timing
-
500
-
ms
-
2006
-
XIN
cycles
Serial Clock Frequency
SCLK
0
-
2
MHz
SCLK Falling to CS Falling for continuous running SCLK
t0
(Note 28)
100
-
-
ns
Serial Clock
SDI Write Timing
Pulse Width High
t1
Pulse Width Low
t2
250
-
250
-
-
ns
-
ns
CS Enable to Valid Latch Clock
Data Set-up Time prior to SCLK rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
SDO Read Timing
t3
50
-
t4
50
-
t5
100
-
t6
100
-
-
ns
-
ns
-
ns
-
ns
CS to Data Valid
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
t7
-
-
150
ns
t8
-
-
150
ns
t9
-
-
150
ns
Notes: 25. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 200 kHz
(CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput.
26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
28. Applicable when SCLK is continuously running.
Specifications are subject to change without notice.
DS317F2
11
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