CS5351 Просмотр технического описания (PDF) - Cirrus Logic
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CS5351 Datasheet PDF : 23 Pages
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4.2.2
CS5351
Master Mode
In Master Mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in Figure 23. Refer to Table 3 for common master clock frequencies.
÷ 256
Single
Speed
00
MCLK
÷1
0
÷2
1
÷ 128
Double
Speed
01
÷ 64
Quad
Speed
10
LRCK Output
(Equal to Fs)
M1 M0
MDIV
÷4
Single
Speed
00
÷2
Double
Speed
01
÷1
Quad
Speed
10
SCLK Output
Figure 23. CS5351 Master Mode Clocking
SAMPLE RATE (kHz)
32
44.1
48
64
88.2
96
176.4
192
MDIV = 0
MCLK (MHz)
8.192
11.2896
12.288
8.192
11.2896
12.288
11.2896
12.288
MDIV = 1
MCLK (MHz)
16.384
22.5792
24.576
16.384
22.5792
24.576
22.5792
24.576
Table 3. CS5351 Common Master Clock Frequencies
4.3 Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-
lay between the release of reset and the generation of valid output due to the finite output impedance of
FILT+ and the presence of the external capacitance.
DS565F2
17
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