CS5351
SCLK output
LRCK
output
SDOUT
tmslr
tsdo
MSB
CLK input
tslrd
LRCK input
MSB-1
SDOUT
tsclkw
MSB
MSB-1
tdss
MSB-2
Figure 13. Master Mode, Left-Justified SAI
Figure 14. Slave Mode, Left-Justified SAI
SCLK input
tslrd
LRCK input
SDOUT
tsclkw
SCLK input
tslrd
tdss
MSB
MSB-1
LRCK input
SDOUT
tsclkw
tdss
MSB
MSB-1
Figure 15. Master Mode, I²S SAI
Figure 16. Slave Mode, I²S SAI
LRCK
OVFL
t setup
t hold
Figure 17. OVFL Output Timing
12
DS565F2