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CL-PS7111

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

Figure 3-2 shows a simplified functional block diagram of the CL-PS7111. All external memory and

peripheral devices are connected to the 8-, 16-, or 32-bit data bus, using the external 28-bit address bus

and control signals. Bus transfer times can be extended by using the EXPRDY signal to lengthen bus

cycles. The maximum burst transfer rate of the external bus is approximately 70 Mbytes per sec. using

32-bit-wide DRAM at 18.432 MHz or 25 Mbytes per sec. using 16-bit-wide DRAM at 13 MHz.

13-MHZ INPUT

3.6864 MHZ

32.768 KHZ

EINT[1–3], FIQ,

MEDCHG

BATOK, NEXTPWR

PWRFL, BATCHG

PORTS A, B, D (8-BIT)

PORT E (3-BIT)

KEYBOARD COLUMN

DRIVERS (0–7)

BUZZER DRIVE

DC TO DC

ADCCLK, ADCIN,

ADCOUT, SMPCLK,

RXFS, TXFS

PCMCLK, PCMSYNC

PCMIN, PCMOUT,

18.432-MHZ

PLL

32.768-KHZ

OSCILLATOR

INTERRUPT

CONTROLLER

POWER

MANAGEMENT

GPIO

PSU

CONTROL

SYNC. SERIAL

INTERFACE

CODEC INTFC.

ARM710a

ARM7

MP CORE

8-KBYTE

CACHE

MMU

COUNTERS

(2)

RTC

ON-CHIP

BOOT ROM

INTERNAL DATA BUS

STATE

CONTROL

CL-PS6700

INTFC.

ROM/EXPANSION

CONTROL

DRAM

CONTROLLER

INTERNAL

ADDRESS BUS

MUX

LCD

CONTROLLER

SRAM

2 KBYTE

IRDA

UART

UART

D0–D31

NPOR, RUN,

RESET, WAKEUP

PB[0–1], CS[4–5]

EXPCLK, WORD,

CD[0–3], EXPRDY,

WRITE

MOE, MWE, NMOE,

NMWE

NRAS[0–1], NCAS[0–3]

A[0–27],

DRA[0–12]

LCD DRIVE

LED AND PHOTO-

DIODE

ASYNC INTERFACE 1

ASYNC INTERFACE 2

Figure 3-2. CL-PS7111 Block Diagram

September 1997

PRELIMINARY DATA BOOK v2.0

19

FUNCTIONAL DESCRIPTION

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