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CL-PS7111

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

3. FUNCTIONAL DESCRIPTION

The CL-PS7111 is a single-device embedded controller designed to be used in low-cost and low-power

applications such as hand-held personal organizers and hand-held internet browsers. There are other

devices offered by Cirrus Logic (http://www.cirrus.com) that can be used around the CL-PS7111 to build

a complete hand-held organizer, such as the CL-PS6700 PCMCIA controller, fax/modem chipsets, IR

chipsets, codecs, and so on. The CL-PS7111 operates at 2.7 V (at 13.0 MHz) or 3.3 V (at 18.432 MHz).

The various peripheral functions are built around an ARM710a microprocessor with 8 Kbytes of four-way

set-associative cache. At 18.432 MHz the CL-PS7111 delivers approximately 15 MIPS of sustained per-

formance and 18.4 MIPS of peak performance. This is approximately the same as a 33-MHz ’486-based

PC.

The CL-PS7111 design is optimized for low-power dissipation. At 3.3 V and 18.432-MHz clock speed, the

device typically dissipates 66 mW during the ‘operating state’ (all oscillators, PLL, LCD, and processor

clock running), 15 mW in the ‘idle state’ (all oscillators and LCD running, but processor clock is halted),

and 15 µW in the ‘standby state’ (no display and the main oscillator is shut down). At 2.7 V and 13.0 MHz,

the respective values are 45 mW, 9 mW, and 15 µW.

The CL-PS7111 can interface to two banks of DRAM; each bank can be up to 256 Mbytes. There is also

an interface for two ROM/flash and three expansion devices, each up to 256 Mbytes, and an interface to

two CL-PS6700 PCMCIA controllers. The expansion devices could be additional ROM/SRAM/Flash. In

addition, the CL-PS7111 provides 2 Kbytes of on-chip SRAM and internal 128 bytes of boot ROM. The

SRAM may be used for critical program storage as well as LCD frame buffer. The start address of the

frame buffer can reside anywhere in the addressable memory space. A system can therefore be designed

with SRAM only for very low power applications.

The boot ROM is hardware selectable on power-on or reset. This boot ROM initializes UART1 and down-

loads the application-specific main boot code into the on-chip SRAM. Once download is complete, exe-

cution jumps to the start of the on-chip SRAM.

The CL-PS7111 supports a number of serial interfaces including two high-speed (115 kbps) UARTs with

Rx and Tx FIFOs, a codec interfaces with FIFO and an additional synchronous serial interface.

The CL-PS7111 is fabricated in a 0.6-µm CMOS process and is fully static. The CL-PS7111 is available

in a 208-pin VQFP package.

Figure 3-1 shows a system-level block diagram for the CL-PS7111. As is shown, all the peripherals (such

as the LCD module, keyboard, PCMCIA socket, and so on) can be added without any glue logic.

16

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

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