IDT72V3670L10PFI Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3670L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

tCLKH

tCLKL

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

WEN

tENS

tENH

PAE

n words in FIFO(2),

n + 1 words in FIFO(3)

RCLK

REN

NOTES:

1. n = PAE offset.

2. For IDT Standard Mode.

3. For FWFT Mode.

4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.

5. Select this mode by setting PFM LOW during Master Reset.

tPAEA

n + 1 words in FIFO(2),

n + 2 words in FIFO(3)

tPAEA

tENS

n words in FIFO(2),

n + 1 words in FIFO(3)

4667 drw 26

Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

WCLK

tCLKH

tCLKL

WEN

tENS

tENH

tHF

D/2 + 1 words in FIFO(1),

HF

D/2 words in FIFO(1),

[ ] D2-1+ 1 words in FIFO(2)

[ ] D-1

2 +2

words in FIFO(2)

D/2 words in FIFO(1),

[ ] D-1

2 +1

words in FIFO(2)

tHF

RCLK

tENS

REN

4667 drw 27

NOTES:

1. In IDT Standard mode: D = maximum FIFO depth. D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the

IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.

2. In FWFT mode: D = maximum FIFO depth. D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680,

32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.

Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)

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