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IDT72V3670L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tCLKH

WCLK

WEN

tCLKL

tENS

tENH

PAE

RCLK

REN

n words in FIFO (2),

n+1 words in FIFO (3)

tSKEW2(4) tPAES

1

2

n+1 words in FIFO (2),

n+2 words in FIFO (3)

tENS

1

tENH

tPAES

2

n words in FIFO (2),

n+1 words in FIFO (3)

4667 drw 24

NOTES:

1. n = PAE offset.

2. For IDT Standard mode

3. For FWFT mode.

4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of

WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.

5. PAE is asserted and updated on the rising edge of WCLK only.

6. Select this mode by setting PFM HIGH during Master Reset.

Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

WCLK

tCLKH

tCLKL

WEN

tENS

tENH

PAF

RCLK

D - (m + 1) words in FIFO

tPAFA

D - m words

in FIFO

tPAFA

D - (m + 1) words

in FIFO

tENS

REN

4667 drw25

NOTES:

1. m = PAF offset.

2. D = maximum FIFO Depth.

In IDT Standard Mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the

IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.

In FWFT Mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690,

65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.

3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.

4. Select this mode by setting PFM LOW during Master Reset.

Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

32

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