IDT72V3670L10PFI Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3670L10PFI Datasheet PDF : 36 Pages
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
t CLKH
t CLK
t CLKL
t LDS
t LDH
t LDH
LD
WEN
t ENS
t ENH
t ENH
t DS
t DH
t DH
D0 - Dn
PAE
OFFSET
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
PAF
OFFSET
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
4667 drw 21
RCLK
LD
t CLKH
t CLK
t CLKL
t LDS
t LDH
t LDH
REN
t ENS
t ENH
t ENH
Q0 - Qn
DATA IN OUTPUT REGISTER
tA
tA
PAE OFFSET
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
PAF OFFSET
4667 drw 22
tCLKL
tCLKL
WCLK
WEN
PAF
tENS
1
tENH
D - (m+1) words in FIFO(2)
2
1
2
tPAFS
tSKEW2(3)
D - m words in FIFO(2)
tPAFS
D-(m+1) words
in FIFO(2)
RCLK
tENS
tENH
REN
4667 drw 23
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768
for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690,
65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
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