MX28F2100B Просмотр технического описания (PDF) - Macronix International
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MX28F2100B Datasheet PDF : 45 Pages
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MX28F2100B
ERASE RESUME
This command will cause the command register to clear
the suspend state and set DQ6, DQ7, back to 0, 0, but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all other
conditions.
SET-UP AUTOMATIC PROGRAM/PROGRAM
COMMANDS
The Automatic Set-up Program is a command only
operation that stages the device for automatic pro-
gramming. Automatic Set-up Program is performed by
writing XX10H/XX40H to the command register.
Program command is the command for byte-program
or word-program.
Once the Automatic Set-up Program operation is per-
formed, the next WE pulse causes a transition to an
active programming operation. Addresses are latched
on the falling edge, and data are internally latched on
the rising edge of the WE pulse. The rising edge of WE
also begins the programming operation. The system is
not required to provide further controls or timings. The
device will automatically provide an adequate
internally generated program pulse and verify margin.
If the program opetation was unsuccessful, bit 4 of the
Status Register will be set to a "1", indicating a
program failure. If Vpp was not within acceptable limits
after the program command is issued, the state
machine will not execute a program sequence; in
stead, bit 4 of the Status Register is set to a "1" to
indicate a Program Failure, and bit 3 is set to a "1" to
identify that Vpp supply voltage was not within
acceptable limits.
STATUS REGISTER
The device contains a Status Register which may be
read to determine when a Program or Erase operation
is complete, and whether that operation completed
successfully. The Status Register may be read at any
time by writing the Read Status command to the
command interface. After writing this command, all
subsequent Read operations output data from the
Status Register until another command is written to the
command interface. A Read Array command must be
written to the command interface to return to the read
array mode.
The Status Register bits are output on DQ[0:7],
whether the device is in the byte-wide (x8) or word-
wide (x16) mode. In the word-wide mode the upper
byte, DQ[8:15], is set to 00H during a Read Status
command. In the byte-wide mode, DQ[8:14] are tri-
stated and DQ15/A-1 retains the low order address
function.
The contents of the Status Register are latched on the
falling edge of OE or CE, whichever occurs last in the
read cycle. This prevents possible bus errors which
might occur if the contents of the Status Register
change while reading the Status Register. CE or OE
must be toggled with each subsequent status read, or
the completion of a Program or Erase operation will not
be evident from the Status Register.
When the state machine is active, this register will
indicate the status of the state machine, and will also
hold the bits indicating whether or not the state
machine was successful in performing the desired
operation.
CLEARING THE STATUS REGISTER
The state machine sets status bits "3" through "7" to
"1", and clears bits "6" and "7" to "0", but cannot clear
status bits "3" through "5" to "0". Bits 3 through 5 can
only be cleared by the controlling CPU through the use
of the Clear Status Register command. These bits can
indicate various error conditions. By allowing the
system software to control the resetting of these bits,
several operations may be performed (such as
cumulatively programming several bytes or erasing
multiple blocks in sequence). The Status Register may
then be read to determine if an error occurred during
that programming or erasure series. This adds
flexibility to the way the device may be programmed or
erased. Once an error occured, the command
Interface Only responds to clear Status Register, Read
Status Register and Read Array. To clear the Status
Register, the Clear Status Register command is written
to the command interface. Then, any other command
may be issued to the command interface. Note, again,
that before read cycle can be initiated, a Read Array
command must be written to the command interface to
specify whether the read data is to come from the
Memory Array, Status Register, or Sili-con -ID.
P/N: PM0382
REV. 1.5, MAR. 24, 1998
9
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