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MX28F2100B

2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY

Macronix International 

MX28F2100B

READ COMMAND

While VPP is high, for erasure and programming,

memory contents can also be accessed via the Read

command. The read operation is initiated by writing

XXFFH into the command register. Microprocessor

read cycles retrieve array data. The device remains

enabled for reads until the command register contents

are altered.

RESET COMMAND

A Reset command is provided as a means to safely

abort the erase- or program-command sequences.

Following Set-up command with two consecutive

writes of XXFFH for ERS (or one write of XXFFH for

PGM) will safely abort the operation. Memory contents

will not be altered. A valid command must then be

written to place the device in the desired state.

SILICON-ID-READ COMMAND

Flash-memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer- and device-codes must be accessible

while the device resides in the target system. PROM

programmers typically access signature codes by rais-

ing A9 to a high voltage. However, multiplexing high

voltage onto address lines is not a desired system-

design practice.

The MX28F2100B contains a Silicon-ID-Read

operation to supplement traditional PROM-

programming methodology. The operation is initiated

by writing XX90H into the command register.

Following the command write, a read cycle with

A0=VIL retrieves the manufacturer code of

C2H(BYTE=VIL, 00C2H(BYTE=VIH). A read cycle

with A0=VIH returns the device code of 2BH(BYTE =

VIL), 002BH(BYTE = VIH).

ERASE-VERIFY COMMAND

After each erase operation, all bytes must be verified.

The Erase Verify operation is initiated by writing

XXA0H into the command register. The address for

the byte to be verified must be supplied as it is latched

on the falling edge of the WE pulse.

The MX28F2100B applies an internally generated

margin voltage to the addressed byte. Reading

FFFFH from the addressed byte indicates that all bits

in the byte are erased.

The Erase-Verify command must be written to the

command register prior to each byte verification to

latch its address. The process continues for each byte

in the array until a byte does not return FFFFH data, or

the last address is accessed.

In the case where the data read is not FFFFH, another

erase operation needs to be performed. (Refer to Set-

up Erase/Erase). Verification then resumes from the

address of the last-verified byte. Once all bytes in the

array have been verified, the erase step is complete.

The device can be programmed. At this point, the

verify operation is terminated by writing a valid

command (e.g. Program Set-up) to the command

register. The High Reliability Erase algorithm

illustrates how commands and bus operations are

combined to perform electrical erasure of the

MX28F2100B.

SET-UP AUTOMATIC CHIP ERASE/ERASE

COMMANDS

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to excuting the

Automatic Set-up Erase command and Automatic Chip

Erase command. Upon executing the Automatic Chip

Erase command, the device automatically will

program and verify the entire memory for an all-zero

data pattern. When the device is automatically verified

to contain an all-zero pattern, a self-timed chip erase

and verify begin. The erase and verify operations are

completed by the feed back of the status register. The

system is not required to provide any control or timing

during these operations.

P/N: PM0382

REV. 1.5, MAR. 24, 1998

7

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