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SMJ55161

262144 BY 16-BIT MULTIPORT VIDEO RAM

Austin Semiconductor 

SMJ55161

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS056D – MAY 1995 – REVISED OCTOBER 1997

column-address strobe (CASL, CASU)

CASL and CASU are control inputs that latch the states of the column address and DSF to control DRAM and

transfer functions of the SMJ55161. CASx also acts as output enable for the DRAM output pins DQ0 – DQ15.

In DRAM operation, CASL enables data to be written to or read from the lower byte (DQ0 – DQ7), and CASU

enables data to be written to or from the upper byte (DQ8 – DQ15). In transfer operations, address bits A0 – A8

are latched at the first falling edge of CASx as the start position (tap) for the serial-data output (SQ0 – SQ15).

output enable/transfer select (TRG)

TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as

RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0 – DQ15.

For transfer operation, TRG must be brought low before RAS falls.

write-mask select, write enable (WE)

In DRAM operation, WE enables data to be written to the DRAM. WE is also used to select the DRAM

write-per-bit mode. Holding WE low on the falling edge of RAS invokes the write-per-bit operation. The

SMJ55161 supports both the nonpersistent write-per-bit mode and the persistent write-per-bit mode.

special-function select (DSF)

The DSF input is latched on the falling edge of RAS or the first falling edge of CASx, similar to an address. DSF

determines which of the following functions are invoked on a particular cycle:

D CBR refresh with reset (CBR)

D CBR refresh with no reset (CBRN)

D CBR refresh with no reset and stop-point set (CBRS)

D Block write

D Loading write-mask register for the persistent write-per-bit mode (LMR)

D Loading color register for the block-write mode

D Split-register-transfer read

DRAM data I/O, write mask data (DQ0 – DQ15)

DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct

TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity

as data in. During a normal access cycle, the outputs remain in the high-impedance state until TRG is brought

low. Data appears at the outputs until TRG returns high, CASx returns high following RAS returning high, or RAS

returns high following CASx returning high. The write mask is latched into the device through the random DQ

pins by the falling edge of RAS and is used on all write-per-bit cycles. In a transfer operation, the DQ outputs

remain in the high-impedance state for the entire cycle.

serial-data outputs (SQ0 – SQ15)

Serial data is read from the SQ pins. The SQ output buffers provide direct TTL compatibility (no pullup resistors)

with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state as long

as the serial-enable pin, SE, is high. The serial outputs are enabled when SE is brought low.

serial clock (SC)

Serial data is accessed out of the data register during the rising edge of SC. The SMJ55161 is designed to work

with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the

data registers that comprise the SAM are static. There is also no minimum SC-clock operating frequency.

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