SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
functional operation description
Table 1 lists the DRAM and SAM functions, summarizing Table 3 and Table 4.
Table 1. DRAM and SAM Functions
FUNCTION
RAS FALL
CASx‡ TRG WE
CASx
FALL
ADDRESS
DSF DSF RAS CASx§
DQ0 – DQ15†
RAS
CASL
CASU
WE
MNE
CODE
Reserved (do not use)
L
L
L
L
X
X
X
X
X
—
CBR refresh (no reset) and stop-point
set¶
L
X
L
H
X
Stop
Point #
X
X
X
CBRS
CBR refresh (option reset)||
L
X
H
L
X
X
X
X
X
CBR
CBR refresh (no reset)k
L
X
H
H
X
X
X
X
X
CBRN
Full-register-transfer read
H
L
H
L
X
Row
Address
Tap
Point
X
X
RT
Split-register-transfer read
H
L
H
H
X
Row
Address
Tap
Point
X
X
SRT
DRAM write
(nonpersistent write-per-bit)
H
H
L
L
L
Row Column Write
Address Address Mask
Valid
Data
RWM
DRAM block write
(nonpersistent write-per-bit)
H
H
L
L
H
Row
Address
Block
Address
A2 – A8
Write
Mask
Column
Mask
BWM
DRAM write
(persistent write-per-bit)
H
H
L
L
L
Row Column
Address Address
X
Valid
Data
RWM
DRAM block write
(persistent write-per-bit)
H
H
L
L
H
Row
Address
Block
Address
A2 – A8
X
Column
Mask
BWM
DRAM write (nonmasked)
H
H
H
L
L
Row Column
Address Address
X
Valid
Data
RW
DRAM block write (nonmasked)
H
H
H
L
H
Row
Address
Block
Address
A2 – A8
X
Column
Mask
BW
Load write-mask registerh
H
H
H
H
L
Refresh
Address
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Address
X
X
Color
Data
LCR
Legend:
Col Mask = H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
X
= Don’t care
† DQ0 – DQ15 are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later.
‡ Logic L is selected when either or both CASL and CASU are low.
§ The column address and block address are latched on the first falling edge of CASx.
¶ CBRS cycle should be performed immediately after the powerup initialization cycle.
# A0 – A3, A8: don’t care; A4 – A7: stop-point code
|| CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
kCBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
hLoad-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
7