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AM79C970A

PCnet™-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product

Advanced Micro Devices 

APPENDIX E

PCnet-PCI II and PCnet-PCI

Differences

OVERVIEW

This appendix summarizes the enhancements of the

Am79C970A PCnet-PCI II controller over the

Am79C970 PCnet-PCI controller. The feature sum-

mary is followed by a detailed list of all register bit

changes. The document also compares the pinout of

the PCnet-PCI II controller with the pinout of the PC-

net-PCI and the Am79C974 PCnet-SCSI (also known

as Golden Gate) to show that the Flex-I/O footprint is

continued to be supported.

NEW FEATURES

n Three Volt support for PCI bus interface

n Full Duplex Ethernet

n 272-byte Transmit FIFO, 256-byte Receive FIFO

n Enhanced PCI bus transfer cycles:

— No more address stepping

— Initialization Block read in non-burst (default) or

burst mode

— Added new software style and reordered the de-

scriptor entries to allow burst transfers for both,

descriptor read and write accesses

— FIFO DMA bursts length programmable from 1

to indefinite

— Type of memory command for burst read trans-

fers programmable to be either Memory Read

Line or Memory Read Multiple (controlled by

MEMCMD, BCR18, bit 9)

— Support for fast back-to-back slave transactions

even when the first transaction is addressing a

different target MEMCMD, BCR18, bit 9)

— Enhanced disconnect of I/O burst access

n Allows I/O resources to be memory mapped

n Eight-bit programmable PCI Latency Timer.

MIN_GNT and MAX_LAT programmable via

EEPROM

n System interrupt for data parity error, master abort

or target abort in master cycles

n Network activity is terminated in an orderly se-

quence after a master or target abort

n Advanced parity error handling. Mode has enable

bit and status bit in RMD1 and TMD1. All network

activity is terminated in an orderly sequence. Will

only work with 32-bit software structures.

n All registers in the PCI configuration space are

cleared by H_RESET

n Expansion ROM interface supporting devices of up

to 64 K x 8. One external address latch is required.

n Reading from the S_RESET port returns TRDY

right away

n REQ deassertion programmable to adapt to the re-

quirements of some embedded systems

n INTA pin programmable for pulse mode to adapt to

the requirements of some embedded systems

n Some previously reserved locations in the

EEPROM map are now used for new features

n Suspend mode for graceful stop and access to the

CSR without reinitialization

n User Interrupt

n Reduced number of transmit interrupts:

— Transmit OK disable (CSR5, bit 15). When bit is

set to ONE, a transmit interrupt is only gener-

ated on frames that suffer an error.

— Last Transmit Interrupt. TMD1, bit 28 is read by

the PCnet-PCI II controller to determine if an in-

terrupt should be generated at the end of the

frame. Only interrupts for successful transmis-

sion can be suppressed. Enabled by LTINTEN

(CSR5, bit 14).

n Disable Transmit Stop on Underflow (CSR3, bit 6)

bit. PCnet-PCI controller recovers automatically

from transmit underflow.

n Interrupt indication when coming out of sleep mode

n Interrupt indication for Excessive Deferral

n Address match information in Receive Descriptor

n Asserting SLEEP shuts down the entire device

n S_RESET (reading the RESET register) does not

affect the TMAU, except for the T-MAU in snooze

mode

n LED registers programmable via EEPROM.

n Magic Packet Mode

n EADI interface. Multiplexed with the same LED pins

as for the Am79C965 PCnet-32.

Am79C976

213

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